Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Hardware designs for integrated circuits can be synthesized from high-level descriptions. For example, descriptions may be made at an algorithm level using hardware description languages or programming languages. The descriptions can be synthesized into designs at a module level, a register transfer level (RTL), a gate level, or a transistor level. A hardware design involving signal processing may be abstracted as a data flow graph (DFG).
Scheduling and binding are part of hardware synthesis. Scheduling involves partitioning functionality of a circuit into steps to be performed. For example, the steps can be states of a finite state machine (FSM) or operations performed on signal samples within a signal processing circuit. Binding maps functionality onto hardware resources within the integrated circuit.
Technology scaling to smaller integrated circuit feature sizes causes increases in power density or power consumed per unit area. Increases in localized power consumption within an integrated circuit can result in hot regions on the chip. Having regions of differing temperature introduces heat gradients. Heat gradients result in thermal stress that can increase chip aging due to negative bias temperature instability, electromigration, or gradual dielectric breakdown. These factors degrade circuit reliability. Performance of the chip may also diminish when increased temperature slows carrier mobility, lowers transistor switching speed, and increases interconnect resistance.
Many design and operational considerations for complex electronic systems attempt to reduce power consumption. However, power consumption optimization and thermal optimization are not interchangeable since power optimization attempts to minimize average power consumption, but may support the formation of local thermal hotspots. A critical hotspot can damage the chip without significantly increasing average power. Techniques for lowering static or dynamic power consumption at the chip level may reduce overall power usage while power gradients or hotspots may remain or even increase because of global power reduction attempts.